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[VHDL-FPGA-Verilog] uart_verilog

Description: uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
Platform: | Size: 10240 | Author: lfy | Hits:

[Embeded-SCM Develop] fpga_digit_serial_arithmetic_1

Description: fpga/CPLD开发管理Digit-Serial DSP Functions-fpga/CPLD Development and Management of Digit-Serial DSP Functions
Platform: | Size: 2659328 | Author: liuandy | Hits:

[VHDL-FPGA-Verilog] 8251Verilog

Description: 通用串行异步收发器8251的Verilog HDL源代码,经过仿真验证。 -Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code, through simulation.
Platform: | Size: 15360 | Author: 钟兵 | Hits:

[VHDL-FPGA-Verilog] chuangbingzhuanhuan

Description: 一个用verilog写的串行传输到并行传输的程序，在quaters下编的-Using Verilog to write a serial transmission to the parallel transmission of the procedure, under the quaters
Platform: | Size: 24576 | Author: 王金栓 | Hits:

[VHDL-FPGA-Verilog] uart_regs

Description: 此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.
Platform: | Size: 776192 | Author: 江 | Hits:

[Com Port] UART

Description: UART_verilog,自己设计的异步串行收发。包括测试文件。-UART_verilog, designed to send and receive asynchronous serial. Including the test file.
Platform: | Size: 6144 | Author: 甲壳虫 | Hits:

[Other Embeded program] I2C_extender

Description: verilog编写，将I2C串行数据转化为并行数据的功能模块，类似于PCF8574芯片的功能。以后不用买另外的芯片就可以直接将并行数据连到I2C总线上了-Verilog prepared to I2C serial data into parallel data of the function modules, similar to the function of PCF8574 chip. After the chips do not have to buy another can be connected directly to the parallel data to the I2C bus on the
Platform: | Size: 1024 | Author: 苗苗 | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: 简化的串口通信，去掉了奇偶校验位，波特率为9600，测试通过，fpga型号为xinlinx vp20-Simplified serial communication, removing the parity bit, the baud rate to 9600, test, fpga model xinlinx vp20
Platform: | Size: 5120 | Author: 刘红亮 | Hits:

[VHDL-FPGA-Verilog] veriloguartrx

Description: verilogHDL编写的串口检测程序，自己写的，相对其他的代码，本程序比较简短，初学者容易掌握。-verilogHDL prepared by serial testing procedures, their own writing, compared with other code, the procedure relatively brief, easy to grasp for beginners.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] SPI_verilog_vhdl

Description: SPI串口的内核实现 分verilog和HDLC实现-SPI serial kernel realize realize sub-Verilog and HDLC
Platform: | Size: 13312 | Author: qian | Hits:

[VHDL-FPGA-Verilog] tx

Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send.
Platform: | Size: 7168 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] rxd

Description: 自己编写的串口UART的接收Verilog模块，支持中断和查询方式接收，对信号的畸变适应能力强。-I have written serial UART reception Verilog modules, support and inquiries receive interrupt signal distortion adaptable.
Platform: | Size: 2048 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] UART

Description: UART 串口程序，verilog语句，很好的实现了UART的通信功能！-UART serial procedures, verilog statement, very good communication to achieve the UART function!
Platform: | Size: 182272 | Author: 王和国 | Hits:

[VHDL-FPGA-Verilog] spi.tar

Description: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Platform: | Size: 116736 | Author: hcjian | Hits:

[Other Embeded program] uart_rx

Description: actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码-actel A3P250 fpga with VERILOG HDL Serial functional language source code
Platform: | Size: 533504 | Author: wuqj | Hits:

[Com Port] RS232

Description: FPGA实现RS-232串口收发的Verilog程序，已经调通。-FPGA realization of RS-232 serial port to send and receive the Verilog procedures, Qualcomm has been transferred.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog实现的串口异步通信，适用于RS232-Using Verilog realization of serial asynchronous communication, applied to RS232
Platform: | Size: 1126400 | Author: 王权 | Hits:

[Crack Hack] aes_core

Description: Verilog实现AES加密算法 密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用-AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied
Platform: | Size: 79872 | Author: yuansuchun | Hits:

[VHDL-FPGA-Verilog] Serial_CRC

Description: CRC校验串行实现方法,verilog源码,利用反馈线性移位寄存器的方法,实现简单,适用于串行通信协议中的CRC校验.-CRC checksum method of serial realize, verilog source code, the use of linear feedback shift register method, the realization of simple serial communication protocol for the CRC checksum.
Platform: | Size: 1024 | Author: 徐亮 | Hits:

[mpeg mp3] +++ANNEX_AB

Description: mp3编码器1，根据mp3标准编写，串行结构，c语言，具有比较好的可读性。-mp3 encoder 1, in accordance with the standard preparation of mp3, serial structure, c language, has a better readability.
Platform: | Size: 27648 | Author: libaiqsl | Hits:
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